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8-bit, 500 msps, 1.8 v analog-to-digital converter ad9484 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features snr = 47 dbfs at f in up to 250 mhz at 500 msps enob of 7.5 bits at f in up to 250 mhz at 500 msps (?1.0 dbfs) sfdr = 79 dbc at f in up to 250 mhz at 500 msps (?1.0 dbfs) integrated input buffer excellent linearity dnl = 0.1 lsb typical inl = 0.1 lsb typical lvds at 500 msps (ansi-644 levels) 1 ghz full power analog bandwidth on-chip reference, no external decoupling required low power dissipation 670 mw at 500 mspslvds sdr output programmable (nominal) input voltage range 1.18 v p-p to 1.6 v p-p, 1.5 v p-p nominal 1.8 v analog and digital supply operation selectable output data format (offset binary, twos complement, gray code) clock duty cycle stabilizer integrated data capture clock applications wireless and wired broadband communications cable reverse path communications test equipment low cost digital oscilloscopes satellite subsystems power amplifier linearization functional block diagram agnd pwdn v ref a vdd vin+ vin? cml track-and-hold reference adc core output staging lvds clk+ clk? clock management serial port sclk/dfs sdio csb dco? dco+ or? or+ d7 to d0 drgnd drvdd 8 8 ad9484 09615-001 figure 1. general description the ad9484 is an 8-bit, monolithic, sampling analog-to-digital converter (adc) optimized for high performance, low power, and ease of use. the part operates at up to a 500 msps conver- sion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. all necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. the vref pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the spi port). the adc requires a 1.8 v analog voltage supply and a differen- tial clock for full performance operation. the digital outputs are lvds (ansi-644) compatible and support twos complement, offset binary format, or gray code. a data clock output is available for proper output data timing. fabricated on an advanced bicmos process, the ad9484 is availa- ble in a 56-lead lfcsp, and is specified over the industrial temperature range (?40c to +85c). this product is protected by a u.s. patent. product highlights 1. high performance. maintains 47 dbfs snr at 500 msps with a 250 mhz input. 2. ease of use. lvds output data and output clock signal allow interface to current fpga technology. the on-chip reference and sample-and-hold provide flexibility in system design. use of a single 1.8 v supply simplifies system power supply design. 3. serial port control. standard serial port interface supports various product functions, such as data formatting, power-down, gain adjust, and output test pattern generation.
ad9484 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dc specifications ......................................................................... 3 ? ac specifications .......................................................................... 4 ? digital specifications ................................................................... 5 ? switching specifications .............................................................. 6 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? typical performance characteristics ........................................... 10 ? equivalent circuits ......................................................................... 13 ? theory of operation ...................................................................... 14 ? analog input and voltage reference ....................................... 14 ? clock input considerations ...................................................... 15 ? power dissipation and power-down mode ........................... 16 ? digital outputs ........................................................................... 16 ? timing ......................................................................................... 17 ? vref ............................................................................................ 17 ? ad9484 configuration using the spi ..................................... 18 ? hardware interface ..................................................................... 18 ? configuration without the spi ................................................ 18 ? memory map .................................................................................. 20 ? reading the memory map table .............................................. 20 ? reserved locations .................................................................... 20 ? default values ............................................................................. 20 ? logic levels ................................................................................. 20 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 23 ? revision history 6/11rev. 0 to rev. a change to general description section ........................................ 1 change to aperture time parameter in table 4 ........................... 6 change to figure 34 ....................................................................... 16 changes to register 17 and register 18 in table 12 .................. 20 3/11revision 0: initial version
ad9484 rev. a | page 3 of 24 specifications dc specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.5 v, unless otherwise noted. table 1 . parameter 1 temp min typ max unit resolution 8 bits accuracy no missing codes full guaranteed offset error 25c 0 mv full ?3.0 +3.0 mv gain error 25c 1.0 % fs full ?5.0 +7.0 % fs differential nonlinearity (dnl) 25c 0.13 lsb full ?0.25 +0.25 lsb integral nonlinearity (inl) 25c 0.1 lsb full ?0.15 +0.15 lsb internal reference vref full 0.71 0.75 0.78 v temperature drift offset error full 18 v/c gain error full 0.07 %/c analog inputs (vin+, vin?) differential input voltage range 2 full 1.18 1.5 1.6 v p-p input common-mode voltage full 1.7 v input resistance (differential) full 1 k input capacitance (differential) full 1.3 pf power supply avdd full 1.75 1.8 1.9 v drvdd full 1.75 1.8 1.9 v supply currents i avdd 3 full 283 300 ma i drvdd 3 /sdr mode 4 full 89 100 ma power dissipation sdr mode 4 full 670 720 mw standby mode full 40 50 mw power-down mode full 2.5 7 mw 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 the input range is programmable through the spi, and the range specified reflects the nominal values of each setting. see the section. memory map 3 i avdd and i drvdd are measured with a ?1 dbfs, 10.3 mhz si ne input at a rated sample rate. 4 single data rate mode; this is the default mode of the ad9484.
ad9484 rev. a | page 4 of 24 ac specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.5 v, unless otherwise noted. table 2. parameter 1 , 2 temp min typ max unit snr f in = 30.3 mhz 25c 47.0 dbfs f in = 70.3 mhz 25c 47.0 dbfs f in = 100.3 mhz 25c 47.0 dbfs full 46.5 dbfs f in = 250.3 mhz 25c 47.0 dbfs f in = 450.3 mhz 25c 46.9 dbfs sinad f in = 30.3 mhz 25c 47.0 dbfs f in = 70.3 mhz 25c 47.0 dbfs f in = 100.3 mhz 25c 47.0 dbfs full 46.4 dbfs f in = 250.3 mhz 25c 47.0 dbfs f in = 450.3 mhz 25c 46.9 dbfs effective number of bits (enob) f in = 30.3 mhz 25c 7.5 bits f in = 70.3 mhz 25c 7.5 bits f in = 100.3 mhz 25c 7.5 bits f in = 250.3 mhz 25c 7.5 bits f in = 450.3 mhz 25c 7.5 bits worst harmonic (second or third) f in = 30.3 mhz 25c ?87 dbc f in = 70.3 mhz 25c ?86 dbc f in = 100.3 mhz 25c ?87 dbc full ?75 dbc f in = 250.3 mhz 25c 83 dbc f in = 450.3 mhz 25c 70 dbc sfdr f in = 30.3 mhz 25c 82 dbc f in = 70.3 mhz 25c 81 dbc f in = 100.3 mhz 25c 82 dbc full 75 dbc f in = 250.3 mhz 25c 79 dbc f in = 450.3 mhz 25c 70 dbc worst other harmonic (sfdr excluding second and third) f in = 30.3 mhz 25c ?82 dbc f in = 70.3 mhz 25c ?81 dbc f in = 100.3 mhz 25c ?82 dbc full ?75 dbc f in = 250.3 mhz 25c 79 dbc f in = 450.3 mhz 25c 77 dbc two-tone imd f in1 = 119.5 mhz, f in2 = 122.5 mhz 25c ?77 dbc analog input bandwidth full power 25c 1 ghz 1 all ac specifications tested by driving clk+ and clk? differentially. 2 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed.
ad9484 rev. a | page 5 of 24 digital specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.5 v, unless otherwise noted. table 3. parameter 1 temp min typ max unit clock inputs logic compliance full cmos/lvds/lvpecl internal common-mode bias full 0.9 v differential input voltage high level input (v ih ) full 0.2 1.8 v p-p low level input (v il ) full ?1.8 ?0.2 v p-p high level input current (i ih ) full ?10 +10 a low level input current (i il ) full ?10 +10 a input resistance (differential) full 8 10 12 k input capacitance full 4 pf logic inputs logic 1 voltage full 0.8 drvdd v logic 0 voltage full 0.2 drvdd v logic 1 input current (sdio, csb) full 0 a logic 0 input current (sdio, csb) full ?60 a logic 1 input current (sclk, pdwn) full 50 a logic 0 input current (sclk, pdwn) full 0 a input capacitance full 4 pf logic outputs 2 v od differential output voltage full 247 454 mv v os output offset voltage full 1.125 1.375 v output coding 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 lvds r termination = 100 .
ad9484 rev. a | page 6 of 24 switching specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.5 v, unless otherwise noted. table 4. parameter temp min typ max unit maximum conversion rate full 500 msps minimum conversion rate full 50 msps clk+ pulse width high (t ch ) 1 full 0.9 11 ns clk+ pulse width low (t cl ) 1 full 0.9 11 ns output (lvdssdr) 1 data propagation delay (t pd ) full 0.85 ns rise time (t r ) (20% to 80%) 25c 0.15 ns fall time (t f ) (20% to 80%) 25c 0.15 ns dco propagation delay (t cpd ) full 0.6 ns data to dco skew (t skew ) full ?0.07 +0.07 ns latency full 15 clock cycles aperture time (t a ) 25c 0.85 ns aperture uncertainty (jitter, t j ) 25c 80 fs rms 1 see . figure 2 timing diagram n ? 1 n n + 2 n + 3 n + 4 n + 5 n + 1 clk+ n ? 15 n ? 14 n ? 13 n ? 12 n ? 11 clk? dco+ dco? dx+ dx? vin+, vin? t a t ch t cl 1/ f s t cpd t skew t pd 09615-002 figure 2. timing diagram
ad9484 rev. a | page 7 of 24 absolute maximum ratings table 5. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to drgnd ?0.3 v to +2.0 v agnd to drgnd ?0.3 v to +0.3 v avdd to drvdd ?2.0 v to +2.0 v d0+/d0? through d7+/d7? to drgnd ?0.3 v to drvdd + 0.2 v dco+, dco? to drgnd ?0.3 v to drvdd + 0.2 v or+, or? to drgnd ?0.3 v to drvdd + 0.2 v clk+ to agnd ?0.3 v to avdd + 0.2 v clk? to agnd ?0.3 v to avdd + 0.2 v vin+ to agnd ?0.3 v to avdd + 0.2 v vin? to agnd ?0.3 v to avdd + 0.2 v sdio/dcs to drgnd ?0.3 v to drvdd + 0.2 v pdwn to agnd ?0.3 v to drvdd + 0.2 v csb to agnd ?0.3 v to drvdd + 0.2 v sclk/dfs to agnd ?0.3 v to drvdd + 0.2 v cml to agnd ?0.3 v to avdd + 0.2 v vref to agnd ?0.3 v to avdd + 0.2 v environmental storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the pcb increases the reliability of the solder joints, maximizing the thermal capability of the package. table 6. package type ja jc unit 56-lead lfcsp_vq (cp-56-5) 23.7 1.7 c/w typical ja and jc are specified for a 4-layer board in still air. airflow increases heat dissipation, effectively reducing ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . esd caution
ad9484 rev. a | page 8 of 24 pin configuration and fu nction descriptions pin 1 indicator 1 dnc 2 dnc 3 d0? 4 d0+ 5 d1? 6 d1+ 7 drvdd 8 drgnd 9 d2? 10 d2+ 11 d3? 12 d3+ 13 d4? 14 d4+ 35 vin+ 36 vin? 37 avdd 38 avdd 39 avdd 40 cml 41 avdd 42 avdd 34 avdd 33 avdd 32 avdd 31 vref 30 avdd 29 pwdn 1 5 d 5 ? 1 6 d 5 + 1 7 d 6 ? 1 9 d 7 ? 2 1 o r ? 2 0 d 7 + 2 2 o r + 2 3 d r g n d 2 4 d r v d d 2 5 s d i o 2 6 s c l k / d f s 2 7 c s b 2 8 d n c 1 8 d 6 + 4 5 c l k ? 4 6 a v d d 4 7 d r v d d 4 8 d r g n d 4 9 d c o ? 5 0 d c o + 5 1 d n c 5 2 d n c 5 3 d n c 5 4 d n c 4 4 c l k + 4 3 a v d d top view (not to scale) pin 0 (exposed paddle) = agnd ad9484 5 5 d n c 5 6 d n c notes 1. dnc = do not connect. do not connect to this pin. 2. agnd and drgnd should be tied to a common quiet ground plane. 3. the exposed p addle must be soldered to a ground plane. 09615-003 figure 3. pin configuration table 7. pin function descriptions pin no. mnemonic description 0 agnd 1 analog ground. the exposed paddle must be soldered to a ground plane. 30, 32 to 34, 37 to 39, 41 to 43, 46 avdd 1.8 v analog supply. 7, 24, 47 drvdd 1.8 v digital output supply. 8, 23, 48 drgnd 1 digital output ground. 35 vin+ analog inputtrue. 36 vin? analog inputcomplement. 40 cml common-mode output. enabled through the spi, this pin provides a reference for the optimized internal bias voltage for vin+/vin?. 44 clk+ clock inputtrue. 45 clk? clock inputcomplement. 31 vref voltage reference internal/input/output. nominally 0.75 v. 1, 2, 28, 51 to 56 dnc do not connect. do not connect to this pin. this pin should be left floating. 25 sdio serial port interface (spi) data input/output. 26 sclk/dfs serial port interface clock (serial port mode)/data format select (external pin mode). 27 csb serial port chip select (active low). 29 pwdn chip power-down. 49 dco? data clock outputcomplement. 50 dco+ data clock outputtrue. 3 d0? d0 complement output (lsb). 4 d0+ d0 true output (lsb). 5 d1? d1 complement output. 6 d1+ d1 true output. 9 d2? d2 complement output. 10 d2+ d2 true output. 11 d3? d3 complement output. 12 d3+ d3 true output. 13 d4? d4 complement output.
ad9484 rev. a | page 9 of 24 pin no. mnemonic description 14 d4+ d4 true output. 15 d5? d5 complement output. 16 d5+ d5 true output. 17 d6? d6 complement output. 18 d6+ d6 true output. 19 d7? d7 complement output (msb). 20 d7+ d7 true output (msb). 21 or? overrange complement output. 22 or+ overrange true output. 1 tie agnd and drgnd to a common quiet ground plane.
ad9484 rev. a | page 10 of 24 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, rated sample rate, t a = 25c, 1.5 v p-p differential input, ain = ?1 dbfs, unless otherwise noted. ?100 ?80 ?60 ?40 ?20 ?10 ?90 ?70 ?50 ?30 0 0 20 40 60 80 100 120 140 160 180 amplitude (dbfs) frequency (mhz) 500msps 30.3mhz at ?1.0dbfs snr: 46.0db enob: 7.5 bits 200 220 240 sfdr: 82dbc 09615-106 figure 4. 64k point single-tone fft; 500 msps, 30.3 mhz ?100 ?80 ?60 ?40 ?20 ?10 ?90 ?70 ?50 ?30 0 0 20 40 60 80 100 120 140 160 180 amplitude (dbfs) frequency (mhz) 500msps 100.3mhz at ?1.0dbfs snr: 46.0db enob: 7.5 bits 200 220 240 sfdr: 83dbc 09615-107 figure 5. 64k point single-tone fft; 500 msps, 100.3 mhz ?100 ?80 ?60 ?40 ?20 ?10 ?90 ?70 ?50 ?30 0 0 20 40 60 80 100 120 140 160 180 amplitude (dbfs) frequency (mhz) 500msps 140.3mhz at ?1.0dbfs snr: 46.0db enob: 7.5 bits 200 220 240 sfdr: 82dbc 09615-108 figure 6. 64k point single-tone fft; 500 msps, 140.3 mhz ?100 ?80 ?60 ?40 ?20 ?10 ?90 ?70 ?50 ?30 0 0 20 40 60 80 100 120 140 160 180 amplitude (dbfs) frequency (mhz) 500msps 270.3mhz at ?1.0dbfs snr: 46.0db enob: 7.5 bits 200 220 240 sfdr: 79dbc 09615-109 figure 7. 64k point single-tone fft; 500 msps, 270.3 mhz ?100 ?80 ?60 ?40 ?20 ?10 ?90 ?70 ?50 ?30 0 0 20 40 60 80 100 120 140 160 180 amplitude (dbfs) frequency (mhz) 200 220 240 09615-110 500msps 450.3mhz at ?1.0dbfs snr: 45.9db enob: 7.5 bits sfdr: 70dbc figure 8. 64k point single-tone fft; 500 msps, 450.3 mhz 55 50 45 40 60 65 70 75 80 85 0 100 200 300 400 500 snr/sfdr (db) analog input frequecy (mhz) sfdr (dbc), t a = ?40c sfdr (dbc), t a =+85c sfdr (dbc), t a =+25c snr (dbfs), t a = ?40c snr (dbfs), t a = +25c snr (dbfs), t a = +85c 09615-111 figure 9. single-tone snr/sfdr vs. input frequency (f in ) and temperature; 500 msps
ad9484 rev. a | page 11 of 24 40 45 50 55 60 65 70 75 80 85 50 100 150 200 250 300 350 400 450 500 550 snr/sfdr (db) sample rate (msps) sfdr (dbc), 30.3mhz sfdr (dbc), 100.3mhz snr (dbfs), 30.3mhz snr (dbfs), 100.3m hz 09615-112 figure 10. snr/sfdr vs. sample rate; 30.3 mhz, 100.3 mhz 40 30 10 20 0 50 60 70 80 90 100 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 snr/sfdr (db) amplitude (db) 09615-211 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (db) figure 11. snr/sfdr vs. input amplitude; 500 msps,140.3 mhz ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0 64 128 192 256 inl (lsb) output code 09615-114 figure 12. inl, 500 msps ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 dnl (lsb) 0 64 128 192 256 output code 09615-115 figure 13. dnl, 500 msps 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.29 lsb rms n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 number of hits (m) bins 09615-116 figure 14. grounded input histogram, 500 msps ?100 ?80 ?60 ?40 ?20 ?10 ?90 ?70 ?50 ?30 0 0 20 40 60 80 100 120 140 160 180 amplitude (dbfs) frequency (mhz) 500msps 119.5mhz at ?7.0dbfs 122.5mhz at ?7.0dbfs 200 220 240 sfdr: 77dbc 09615-215 figure 15. 64k point, two-tone fft; 500 msps, 119.2 mhz, 122.5 mhz
ad9484 rev. a | page 12 of 24 0 10 20 30 40 50 60 70 80 90 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 sfdr (db) amplitude (dbfs) imd3 (dbfs) sfdr (dbfs) sfdr (dbc) 09615-118 figure 16. two-tone sfdr vs. input amplitude; 500 msps, 119.5 mhz, 122.5 mhz 30 40 50 60 70 80 90 1.5 1.6 1.7 1.8 1.9 2.0 snr/sfdr (db) v cm (v) sfdr (dbc) snr (dbfs) 09615-119 figure 17. snr/sfdr vs. common-mode voltage; 500 msps, ain = 140.3 mhz 0 100 200 300 400 500 600 700 800 50 100 150 200 250 300 350 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 power (mw) current (ma) sample rate (msps) i avdd i drvdd total power 09615-120 figure 18. current and power vs. sample rate, ain = 30.3 mhz 30 35 40 45 50 55 60 65 70 75 80 500 600 700 800 900 1000 snr/sfdr (db) frequency (mhz) snr (dbfs) sfdr (dbc) 09615-121 figure 19. snr/sfdr at 500 msps; ain sweep at ?1.0 dbfs
ad9484 rev. a | page 13 of 24 equivalent circuits 0.9v 15k ? 15k ? c lk+ clk? avdd avdd avdd 09615-006 figure 20. clock inputs cml v in+ avdd v boost avdd v in+ avdd 500 ? 500 ? a in + a in ? spi controlled dc 09615-007 figure 21. analog input dc equivalent circuit (v cml = ~1.7 v) sclk/dfs 350 ? 30k ? drvdd drvdd 09615-008 figure 22. equivalent sclk /dfs, pdwn input circuit v in+ v in? 1.3pf 1k ? 09615-025 figure 23. analog input ac equivalentcircuit csb 350? 30k ? drvdd drvdd drvdd 09615-009 figure 24. equivalent csb input circuit d r v dd dx+ v? v+ dx? v+ v? 0 9615-010 figure 25. lvds outputs (dx+, dx?, or+, or?, dco+, dco?) 20k ? (11) (01) (00) (10) spi ctrl v ref select 00 = internal v ref 01 = import v ref 10 = export v ref 11 = not used not used vref a v dd 09615-011 figure 26. equivalent vr ef input/output circuit drvdd sdio 30k ? 350 ? drvdd ctrl 0 9615-012 figure 27. equivalent sdio input circuit
ad9484 rev. a | page 14 of 24 theory of operation the ad9484 architecture consists of a front-end sample-and- hold amplifier (sha) followed by a pipelined switched capacitor adc. the quantized outputs from each stage are combined into a final 8-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample, whereas the remaining stages operate on preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a differential sha that can be ac- or dc-coupled in differential or single-ended mode. the output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power-down, the output buffers enter a high impedance state. analog input and voltage reference the analog input to the ad9484 is a differential buffer. for best dynamic performance, match the source impedances driving vin+ and vin? such that common-mode settling errors are symmetrical. the analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. snr and sinad performance degrades significantly if the analog input is driven with a single-ended signal. a wideband transformer, such as mini-circuits? adt1-1wt, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. both analog inputs are self-biased by an on-chip reference to a nominal 1.7 v. an internal differential voltage reference creates positive and negative reference voltages that define the 1.5 v p-p fixed span of the adc core. this internal voltage reference can be adjusted by means of spi control. see the ad9484 configuration using the spi section for more details. differential input configurations optimum performance is achieved while driving the ad9484 in a differential input configuration. for baseband applications, the ad8138 differential driver provides excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8138 is easily set to avdd/2 + 0.5 v, and the driver can be configured in a sallen-key filter topology to pro- vide band limiting of the input signal. vin+ vin? avdd cml ad8138 523 ? 499 ? 499 ? 499 ? 33 ? 33 ? 49.9 ? 1v p-p 0.1f 20pf ad9484 09615-013 figure 28. differential input configuration using the ad8138 at input frequencies in the second nyquist zone and above, the performance of most amplifiers may not be adequate to achieve the true performance of the ad9484. this is especially true in if undersampling applications where frequencies in the 70 mhz to 100 mhz range are being sampled. for these applications, differential transformer coupling is the recommended input configuration. the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz (mhz), and excessive signal power can cause core saturation, which leads to distortion. in any configuration, the value of the shunt capacitor, c (see figure 30 ), is dependent on the input frequency and may need to be reduced or removed. vin+ vin? 15? 15? 50? 1.5v p-p 0.1f 2pf ad9484 09615-014 figure 29. differential transformercoupled configuration as an alternative to using a transformer-coupled input at frequen- cies in the second nyquist zone, the ad8352 differential driver can be used (see figure 30 ).
ad9484 rev. a | page 15 of 24 ad9484 ad8352 0 ? r 0 ? c d r d r g 0.1f 0.1f 0.1f vin+ vin? cml c 0.1f 0.1f 16 1 2 3 4 5 11 r 0.1f 0.1f 10 8, 13 14 v cc 200 ? 200 ? a nalog input a nalog input 09615-015 figure 30. differential input configuration using the ad8352 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? a d9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 50 ? 1 50 ? 1 clk clk 1 50 ? resistors are optional. clk? clk+ adc ad9484 pecl driver clock input clock input 09615-017 figure 31. differential pecl sample clock 100 ? 0.1f 0.1f 0.1f 0.1f a d9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 50 ? 1 50 ? 1 clk clk 1 50 ? resistors are optional. clk? clk+ adc ad9484 lvds driver clock input clock input 09615-018 figure 32. differential lvds sample clock clock input considerations for optimum performance, drive the ad9484 sample clock inputs (clk+ and clk?) with a differential signal. this signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased at ~0.9 v internally and require no additional bias. if the clock signal is dc-coupled, then the common-mode voltage should remain within a range of 0.9 v. figure 33 shows one preferred method for clocking the ad9484. the low jitter clock source is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the secondary transformer limit clock excursions into the ad9484 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9484 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f clock input 50? 100? clk? clk+ adc ad9484 mini-circuits adt1?1wt, 1:1z xfmr schottky diodes: hsm2812 09615-016 figure 33. transformer-coupled differential clock if a low jitter clock is available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 31 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514/ ad9515 family of clock drivers offers excellent jitter performance. in some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 v cmos signal. in such applications, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 34 ).
ad9484 rev. a | page 16 of 24 optional 100 ? 0.1f 0.1f 0.1f 50 ? 1 1 50 ? resistor is optional. clk? clk+ adc ad9484 v cc 1k ? 1k ? clock input ad951x cmos driver 09615-024 figure 34. single-ended 1.8 v cmos input clock (up to 200 mhz) clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to clock duty cycle. a 5% tolerance is commonly required on the clock duty cycle to maintain dynamic performance characteristics. the ad9484 contains a duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9484. when the dcs is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. the duty cycle stabilizer uses a delay-locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately 15 clock cycles to allow the dll to acquire and lock to the new rate. clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) due only to aperture jitter (t j ) can be calculated by snr degradation = 20 log 10 (1/2 f a t j ) in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 35 ). treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9484. separate the power supplies for clock drivers from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about jitter performance as it relates to adcs (visit www.analog.com ). 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps analog input frequency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) 0 9615-019 figure 35. ideal snr vs. input frequency and jitter power dissipation an d power-down mode as shown in figure 18 , the power dissipated by the ad9484 is proportional to its sample rate. the digital power dissipation does not vary much because it is determined primarily by the drvdd supply and bias current of the lvds output drivers. by asserting pdwn (pin 29) high, the ad9484 is placed in standby mode or full power-down mode, as determined by the contents of serial port register 08. reasserting the pdwn pin low returns the ad9484 to its normal operational mode. an additional standby mode is supported by means of varying the clock input. when the clock rate falls below 50 mhz, the ad9484 assumes a standby state. in this case, the biasing network and internal reference remain on, but digital circuitry is powered down. upon reactivating the clock, the ad9484 resumes normal operation after allowing for the pipeline latency. digital outputs digital outputs and timing the ad9484 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option similar to the ieee 1596.3 standard using the spi. this lvds standard can further reduce the overall power dissipation of the device, which reduces the power by ~39 mw. see the memory map section for more infor- mation. the lvds driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. the ad9484 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. no far-end receiver termination or poor differential trace routing may result in timing errors. it is recommended that the trace length be no longer than 24 inches and that the
ad9484 rev. a | page 17 of 24 differential output traces be kept close together and at equal lengths. an example of the lvds output using the ansi standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths less than 24 inches on regular fr-4 material is shown in figure 36 . figure 37 shows an example of when the trace lengths exceed 24 inches on regular fr-4 material. notice that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is up to the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. 500 ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 ?3 ?2 ?1 0 1 2 3 time (ns) 14 12 10 8 6 4 2 0 ?40 ?20 0 20 40 tie jitter histogram (hits) time (ps) eye diagram: voltage (mv) 09615-020 figure 36. data eye for lvds outputs in ansi mode with trace lengths less than 24 inches on standard fr-4 eye diagram: voltage (mv) 600 ?600 ?400 ?200 0 200 400 ?3?2?10123 time (ns) 12 10 8 6 4 2 0 ?100 0 100 tie jitter histogram (hits) time (ps) 09615-021 figure 37. data eye for lvds outputs in ansi mode with trace lengths greater than 24 inches on standard fr-4 the format of the output data is offset binary by default. an example of the output coding format can be found in table 11 . if it is desired to change the output data format to twos comple- ment, see the ad9484 configuration using the spi section. an output clock signal is provided to assist in capturing data from the ad9484. the dco is used to clock the output data and is equal to the sampling clock (clk) rate. in single data rate mode (sdr), data is clocked out of the ad9484 and must be captured on the rising edge of the dco. see the timing diagram shown in figure 2 for more information. output data rate and pinout configuration the output data of the ad9484 can be configured to drive 12 pairs of lvds outputs at the same rate as the input clock signal (sdr mode). out-of-range (or) an out-of-range condition exists when the analog input voltage is beyond the input range of the adc. or+ and or? (or) are digital outputs that are updated along with the data output corresponding to the particular sampled input voltage. thus, or has the same pipeline latency as the digital data. or is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in figure 38 . or remains high until the analog input returns to within the input range and another conversion is completed. by logically anding or with the msb and its complement, overrange high or underrange low conditions can be detected. 1 0 0 0 0 1 or data outputs or +fs ? 1 lsb +fs ? 1/2 lsb +fs ?fs ?fs + 1/2 lsb ?fs ? 1/2 lsb 1111 1111 1111 0000 0000 0000 1111 1111 1110 0001 0000 0000 09615-022 figure 38. or relation to input voltage and output data timing the ad9484 provides latched data outputs with a pipeline delay of 15 clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. minimize the length of the output data lines and loads placed on them to reduce transients within the ad9484. these transi- ents can degrade the dynamic performance of the converter. the ad9484 also provides a data clock output (dco) intended for capturing the data in an external register. the data outputs are valid on the rising edge of dco. the lowest conversion rate of the ad9484 is 50 msps. at clock rates below 1 msps, the ad9484 assumes the standby mode. vref the ad9484 vref pin (pin 31) allows the user to monitor the on-board voltage reference, or provide an external reference (requires configuration through the spi). the three optional settings are internal v ref (pin is connected to 20 k to ground), export v ref , and import v ref . do not attach a bypass capacitor to this pin. vref is internally compensated and additional loading may impact performance.
ad9484 rev. a | page 18 of 24 ad9484 configuration using the spi the ad9484 spi allows the user to configure the converter for specific functions or operations through a structured register space inside the adc. this gives the user added flexibility to customize device operation depending on the application. addresses are accessed (programmed or readback) serially in 1-byte words. each byte can be further divided into fields, which are documented in the memory map section. there are three pins that define the serial port interface (spi) to this particular adc. they are the sclk/dfs, sdio and csb pins. the sclk/dfs (serial clock) is used to synchronize the read and write data presented the adc. the sdio (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb is an active low control that enables or disables the read and write cycles (see table 8 ). table 8. serial port pins mnemonic function sclk sclk (serial clock) is the serial shift clock in. sclk is used to synchronize serial interface reads and writes. sdio sdio (serial data input/ output) is a dual-purpose pin. the typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame. csb csb (chip select) is an active low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 39 and table 10 . during an instruction phase, a 16-bit instruction is transmitted. data then follows the instruction phase and is determined by the w0 and w1 bits, which is one or more bytes of data. all data is composed of 8-bit words. the first bit of each individual byte of serial data indicates whether this is a read or write command. this allows the serial data input/output (sdio) pin to change direction from an input to an output. data can be sent in msb or in lsb first mode. msb first is default on power-up and can be changed by changing the configuration register. for more information about this feature and others, see the an-877 application note, interfacing to high speed adcs via spi at www.analog.com . hardware interface the pins described in table 8 comprise the physical interface between the programming device of the user and the serial port of the ad9484. the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirec- tional, functioning as an input during the write phase and as an output during readback. this interface is flexible enough to be controlled by either proms or pic? microcontrollers as well. this provides the user with an alternate method to program the adc other than a spi controller. if the user chooses not to use the spi interface, some pins serve a dual function and are associated with a specific function when strapped externally to avdd or ground during device power- on. the configuration without the spi section describes the strappable functions supported on the ad9484. configuration without the spi in applications that do not interface to the spi control registers, the sclk/dfs pin can alternately serve as a standalone cmos- compatible control pin. connect the csb pin to avdd, which disables the serial port interface. table 9. mode selection mnemonic external voltage configuration avdd twos complement enabled sclk/dfs agnd offset binary enabled don?t care don?t care csb t s t dh t high t clk t low t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 sdio don?t care sclk don?t care 09615-023 figure 39. serial port interface timing diagram
ad9484 rev. a | page 19 of 24 table 10. serial timing definitions parameter minimum (ns) description t ds 5 setup time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 setup time between csb and sclk t h 2 hold time between csb and sclk t high 16 minimum period that sclk should be in a logic high state t low 16 minimum period that sclk should be in a logic low state t en_sdio 1 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 39 ) t dis_sdio 5 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 39 ) table 11. output data format input (v) condition (v) offset binary output mode, d7 to d0 twos complement mode, d7 to d0 or vin+ ? vin? < ?0.75 ? 0.5 lsb 0000 0000 1000 0000 1 vin+ ? vin? = ?0.75 0000 0000 1000 0000 0 vin+ ? vin? = 0 1000 0000 0000 0000 0 vin+ ? vin? = 0.75 1111 1111 0111 1111 0 vin+ ? vin? > 0.75 + 0.5 lsb 1111 1111 0111 1111 1
ad9484 rev. a | page 20 of 24 memory map reading the memory map table each row in the memory map table (see table 12 ) has eight address locations. the memory map is roughly divided into three sections: chip configuration register map (address 0x00 to address 0x02), transfer register map (address 0xff), and adc functions register map (address 0x08 to address 0x2a). the addr. (hex) column of the memory map indicates the register address in hexadecimal, and the default value (hex) column shows the default hexadecimal value that is already written into the register. the bit 7 (msb) column is the start of the default hexadecimal value given. for example, hexadecimal address 0x2a, ovr_config, has a hexade cimal default value of 0x01. this means bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. the default value enables the or output. overwriting this default so that bit 0 = 0 disables the or output. for more information on this and other functions, consult the an-877 application note, interfacing to high-speed adcs via spi? user manual at www.analog.com . reserved locations undefined memory locations should not be written to other than with the default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. default values coming out of reset, critical registers are preloaded with default values. these values are indicated in table 12 . other registers do not have default values and retain the previous value when exiting reset. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. table 12. memory map register addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 00 chip_port_config 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles should be mirrored by the user so that lsb or msb first mode registers correctly, regardless of shift mode. 01 chip_id 8-bit chip id, bits[7:0] = 0x6c read only default is a unique chip id, different for each device. this is a read- only register. 02 chip_grade 0 0 0 speed grade: 00 = 500 msps x 1 x x 1 x 1 read only child id used to differentiate graded devices. transfer register ff device_update 0 0 0 0 0 0 0 sw transfer 0x00 synchronously transfers data from the master shift register to the slave. adc functions registers 08 modes 0 0 pdwn: 0 = full (default) 1 = standby 0 0 internal power-down mode: 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = normal (power-up) note that external pdwn pin overrides this setting 0x00 determines various generic modes of chip operation.
ad9484 rev. a | page 21 of 24 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 10 offset 8-bit device offset adjustment [7:0] 0111 111 = +127 codes 0000 0000 = 0 codes 1000 0000 = ?128 codes 0x00 device offset trim: codes are relative to the output resolution. 0d test_io (for user-defined mode only, set bits[3:0] = 1000) 00 = pattern 1 only 01 = toggle p1/p2 10 = toggle p1/0000 11 = toggle p1/p2/ 0000 reset pn23 gen: 1 = on 0 = off (default) reset pn9 gen: 1 = on 0 = off (default) output test mode: 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checker board output 0101 = pn23 sequence 0110 = pn9 0111 = one/zero word toggle 1000 = user defined 1001 = unused 1010 = unused 1011 = unused 1100 = unused (format determined by output_mode) 0x00 when set, the test data is placed on the output pins in place of normal data. set pattern values: p1 = reg 0x19, reg 0x1a p2 = reg 0x1b, reg 0x1c 0f ain_config 0 0 0 0 0 analog input disable: 1 = on 0 = off (default) 0 0 0x00 14 output_mode 0 0 0 output enable: 0 = enable (default) 1 = disable 0 output invert: 1 = on 0 = off (default) data format select: 00 = offset binary (default) 01 = twos complement 10 = gray code 0x00 0 15 output_adjust 0 0 0 0 lvds course adjust: 0 = 3.5 ma (default) 1 = 2.0 ma lvds fine adjust: 001 = 3.50 ma 010 = 3.25 ma 011 = 3.00 ma 100 = 2.75 ma 101 = 2.50 ma 110 = 2.25 ma 111 = 2.00 ma 0x00 0 16 output_phase output clock polarity 1 = inverted 0 = normal (default) 0 0 0 0 0 0 0 0x00 17 flex_output_delay 0 0 0 0 output clock delay: 0000 = 0 0001 = ?1/10 0010 = ?2/10 0011 = ?3/10 0100 = reserved 0101 = +5/10 0110 = +4/10 0111 = +3/10 1000 = +2/10 1001 = +1/10 0x00 shown as fractional value of sampling clock period that is subtracted or added to initial t skew , see figure 2 .
ad9484 rev. a | page 22 of 24 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 18 flex_vref vref select 00 = internal v ref (20 k pull-down) 01 = import v ref (0.59 v to 0.8 v on vref pin) 10 = export v ref (from internal reference) 11 = not used 0 input voltage range setting: 11100 = 1.60 11101 = 1.58 11110 = 1.55 11111 = 1.52 00000 = 1.50 00001 = 1.47 00010 = 1.44 00011 = 1.42 00100 = 1.39 00101 = 1.36 00110 = 1.34 00111 = 1.31 01000 = 1.28 01001 = 1.26 01010 = 1.23 01011= 1.20 01011= 1.18 0x00 19 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 1 lsb. 1a user_patt1_msb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 1 msb. 1b user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 2 lsbs. 1c user_patt2_msb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 2 msbs. 2a ovr_config 0 0 0 0 0 0 0 or enable: 1 = on (default) 0 = off 0x01 2c input coupling 0 0 0 0 0 dc coupling enable 0 0 0x00 default is ac coupling. 1 x = dont care.
ad9484 rev. a | page 23 of 24 outline dimensions compliant to jedec standards mo-220-vlld-2 081809-b top view 1 56 14 15 43 42 28 29 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 6.50 ref seating plane 0.60 max 0.60 max coplanarity 0.08 0.05 max 0.02 nom 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 indicator 8.10 8.00 sq 7.90 7.85 7.75 sq 7.65 0.50 bsc bottom view exposed pad p i n 1 i n d i c a t o r figure 40. 56-lead lead frame chip scale package [lfcsp_vq] 8 mm 8 mm body, very thin quad (cp-56-5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9484BCPZ-500 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-5 ad9484bcpzrl7-500 ?40c to +85c 56-lead lead fr ame chip scale package [lfcsp_vq] cp-56-5 ad9484-500ebz evaluation board 1 z = rohs compliant part.
ad9484 rev. a | page 24 of 24 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09615-0-6/11(a)

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